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HM-6561
March 1997
256 x 4 CMOS RAM
Description
The HM-6561 is a 256 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On-chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The data inputs and outputs are multiplexed internally for common I/O bus compatibility. The HM-6561 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature.
Features
* Low Power Standby . . . . . . . . . . . . . . . . . . . . 50W Max * Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max * Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 200ns Max * Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min * TTL Compatible Input/Output * High Output Drive - 1 TTL Load * On-Chip Address Registers * Common Data In/Out * Three-State Output * Easy Microprocessor Interfacing
Ordering Information
PACKAGE CERDIP TEMPERATURE RANGE -40oC to +85oC 220ns HM1-6561B-9 300ns HM1-6561-9 PKG. NO. F18.3
Pinout
HM-6561 (CERDIP) TOP VIEW
A3 A2 A1 A0 A5 A6 A7 GND E 1 2 3 4 5 6 7 8 9 18 VCC 17 A4 16 W 15 S1 14 DQ3 13 DQ2 12 DQ1 11 DQ0 10 S2
PIN A E W S DQ
DESCRIPTION Address Input Chip Enable Write Enable Chip Select Data In/Out
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
2991.1
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HM-6561 Functional Diagram
A0 A1 A5 A6 A7 A LATCHED ADDRESS REGISTER 5 A 5 L G A D DQ0 A Q LATCH L D DQ1 A Q LATCH L D DQ2 A Q LATCH L D DQ3 A Q LATCH L A L W E A2 S1 S2 A3 A4 3 A 3 A A A GATED COLUMN DECODER AND DATA I / O G 8 8 8 8 GATED ROW DECODER 32 x 32 MATRIX
32
LATCHED ADDRESS REGISTER
NOTES: 1. All lines positive logic-active high. 2. Three-state Buffers: A high output active. 3. Data Latches: L high Q = D and Q latches on falling edge of L. 4. Address Latches and Gated Decoders: Latch on falling edge of E and gate on falling edge of E.
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HM-6561
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage. . . . . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance JA JC CERDIP Package . . . . . . . . . . . . . . . . 74oC/W 18oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-6561B-9, HM6561-9 . . . . . . . . . . . . . . . . . . . .-40oC to +85oC
DC Electrical Specifications
VCC = 5V 10%; TA = -40oC to +85oC (HM-6561B-9, HM-6561-9) LIMITS
SYMBOL ICCSB
PARAMETER Standby Supply Current
MIN -
MAX 10
UNITS A mA A V A A V V V V
TEST CONDITIONS IO = 0mA, VI = VCC or GND, VCC = 5.5V E = 1MHz, IO = 0mA, VCC = 5.5V, VI = VCC or GND, W = GND VCC = 2.0V, IO = 0mA, VI = VCC or GND, E = VCC
ICCOP
Operating Supply Current (Note 1)
-
4
ICCDR
Data Retention Supply Current
-
10
VCCDR II IIOZ VIL VIH VOL VOH
Data Retention Supply Voltage Input Leakage Current Input/Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TA = +25oC PARAMETER Input Capacitance (Note 2) Input/Output Capacitance (Note 2)
2.0 -1.0 -1.0 -0.3 VCC -2.0 2.4
+1.0 +1.0 0.8 VCC +0.3 0.4 -
VI = VCC or GND, VCC = 5.5V VIO = VCC or GND, VCC = 5.5V VCC = 4.5V VCC = 5.5V IO = 1.6mA, VCC = 4.5V IO = -0.4mA, VCC = 5.5V
Capacitance
SYMBOL CI CIO NOTES:
MAX 6 10
UNITS pF pF
TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND
1. Typical derating 1.5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes.
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HM-6561
AC Electrical Specifications
VCC = 5V 10%; TA = -40oC to +85oC (HM-6561B-9, HM-6561-9) LIMITS HM-6561B-9 SYMBOL
(1) TELQV (2) TAVQV (3) TSLQX (4) TSHQZ (5) TELEH (6) TEHEL (7) TAVEL (8) TELAX (9) TDVWH (10) TWHDX (11) TWLDV (12) TWLSH (13) TWLEH (14) TSLWH (15) TELWH (16) TWLWH (17) TELEL
HM-6561-9 MIN 5 300 100 0 50 150 0 30 180 180 180 180 180 400 MAX 300 300 150 150 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TEST CONDITIONS (Notes 1, 3) (Notes 1, 3, 4) (Notes 2, 3) (Notes 2, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3)
PARAMETER Chip Enable Access Time Address Access Time Chip Select Output Enable Time Chip Select Output Disable Time Chip Enable Pulse Negative Width Chip Enable Pulse Positive Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Data Delay Time Chip Select Write Pulse Setup Time Chip Enable Write Pulse Setup Time Chip Select Write Pulse Hold Time Chip Enable Write Pulse Hold Time Write Enable Pulse Width Read or Write Cycle Time
MIN 5 220 100 0 40 100 0 20 120 120 120 120 120 320
MAX 220 220 120 120 -
NOTES: 1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. VCC = 4.5V and 5.5V. 4. TAVQV = TELQV + TAVEL.
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HM-6561 Timing Waveforms
(7) TAVEL A (8) TELAX VALID (17) TELEL (6) TEHEL E W HIGH (1) TELQV (2) TAVQV HIGH Z DQ PREVIOUS DATA (4) TSHQZ S1, S2 (4) TSLQX VALID DATA LATCHED (4) TSHQZ HIGH Z (5) TELEH (6) TEHEL (7) TAVEL
TIME REFERENCE -1 0 1 2 3 4 5
FIGURE 1. READ CYCLE TRUTH TABLE TIME REFERENCE -1 0 1 2 3 4 5 NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high. H L L INPUTS E H S1 H X L L L H X W X H H H H X H A X V X X X X V OUTPUT DQ Z Z X V V Z Z Memory Disabled Cycle Begins, Addresses are Latched Output Enabled Output Valid Output Latched Device Disabled, Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) FUNCTION
The HM-6561 Read Cycle is initiated on the falling edge of E. This signal latches the input address word into on-chip registers. Minimum address setup and hold times must be met. After the required hold time, the address lines may change state without affecting device operation. In order to read the output data E, S1 and S2 must be low and W must be high. The output data will be valid at access time (TELQV).
The HM-6561 has output data latches that are controlled by E. On the rising edge of E the present data is latched and remains latched until E falls. Either or both S1 or S2 may be used to force the output buffers into a high impedance state.
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HM-6561 Timing Waveforms (Continued)
(7) TAVEL A (8) TELAX VALID (17) TELEL (6) TEHEL E (13) TWLEH (15) TELWH W (11) TWLDV DQ (16) TWLWH (9) TDVWH VALID DATA (14) TSLWH (12) TWLSH S1, S2 TIME REFERENCE -1 0 1 2 3 4 5 (10) TWHDX (5) TELEH (6) TEHEL (7) TAVEL NEXT
FIGURE 2. WRITE CYCLE TRUTH TABLE INPUTS TIME REFERENCE -1 0 1 2 3 4 5 NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high. H L L E H S1 H X L L X H X H X X W X X L A X V X X X X V DQ X X X V X X X Memory Disabled Cycle Begins, Addresses are Latched Write Period Begins Data In is Written Write is Completed Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) FUNCTION
The write cycle begins with the E falling edge latching the address. The write portion of the cycle is defined by E, S1, S2 and W all being low simultaneously. The write portion of the cycle is terminated by the first rising edge of any control line, E, S1, S2 or W. The data setup and data hold times (TDVWH and TWHDX) must be referenced to the terminating signal. For example, if S2 rises first, data setup and hold times become TDVS2H and TS2HDX; and are numerically equal to TDVWH and TWHDX. Data input/output multiplexing is controlled by W. Care must be taken to avoid data bus conflicts, where the RAM outputs become enabled when another device is driving the data inputs. The following two examples illustrate the timing required to avoid bus conflicts.
Case 1: Both S1 and S2 Fall Before W Falls. If both selects fall before W falls, the RAM outputs will become enabled. W is used to disable the outputs, so a disable time (TWLQZ = TWLDV) must pass before any other device can begin to drive the data inputs. This method of operation requires a wider write pulse, because TWLDV + TDVWH is greater than TWLWH. In this case TWLSL + TSHWH are meaningless and can be ignored. Case 2: W Falls Before Both S1 and S2 Fall. If one or both selects are high until W falls, the outputs are guaranteed not to enable at the beginning of the cycle. This eliminates the concern for data bus conflicts and simplifies data input timing. Data input may be applied as early as convenient, and TWLDV is ignored. Since W is not used to
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HM-6561
disable the outputs it can be shorter than in Case 1; TWLWH is the minimum write pulse. At the end of the write period, if W rises before either select, the outputs will enable, reading data just written. They will not disable until either select goes high (TSHQZ).
IF CASE 1 Both S1 and S2 = Low Before W = Low W = Low Before Both S1 and S2 = Low OBSERVE TWLQZ TWLDV TDVWH TWLWH TDVWH IGNORE TWLWH
If a series of consecutive write cycles are to be performed, W may remain low until all desired locations are written. This is an extension of Case 2. Read-Modify-Write cycles and Read-Write-Read cycles can be performed (extension of Case 1). In fact data may be modified as many times as desired with E remaining low.
CASE 2
TWLQZ TWLDV
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